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ST626X-EMU2
REAL TIME EMULATION DEVELOPMENT TOOLS FOR ST620x/1x/2x/5x/6x MCUs
HARDWARE FEATURES s Supports ST62 and ST63 family s Real time emulation s 32 KBytes of emulation memory s Breakpoint on a single address or on an address area s Break events can be defined on Program Space, Data space mixed with up to 4 external signals s 2 full programmable output for synchronisation s Read/Write registers on the fly (without wait state) s Selective trace in Range or Start/Stop s Break on Stack Overflow s 1K of real trace memory s Tracing of up to 32 bits including 4 external signals SOFTWARE FEATURES s Symbolic debugger at source level s On-line assembler/disassembler s Log files capable of storing any displayed screen s Command files able to execute a set of debugger commands
February 1998
This is advance information from STMicroelectronics. Details are subject to change without notice.
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Table of Contents
ST626X-EMU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 DELIVERY CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 ST6 HDS2 NEW MAINFRAME EMULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 MAIN BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 ST6 HDS2 MAIN BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2.1 External output: OUT1 and OUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Data acquisition signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 LEDs RUN, STOP, WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 INSTALLING THE PROBE: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 7 8
2.4 INSTALLING AN ST6 EMU2 DEVELOPMENT TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 INSTALLING A ST626X-DBE DEDICATION BOARD IN AN ST6 HDS2 . . . . . . . . . . . . . . . 8 2.6 COMPONENTS LAYOUT OF ST6 MAIN BOARD (MB097) . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 COMPONENTS LAYOUT OF ST6 MAIN BOARD (MB174) . . . . . . . . . . . . . . . . . . . . . . . 10 3 ST6 MAINFRAME EMULATOR (FIRST GENERATION) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 MOTHER BOARD (CLZ80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 REAL TIME BOARD (GPFM/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 INTERFACE BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 ST626X-EMU DEVELOPMENT TOOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 INSTALLING ST626X-DBE DEDICATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 INSTALLING THE PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 DEDICATION BOARD (DBE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 VOLTAGE FUNCTIONING RANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 JUMPER DESCRIPTION ON DEDICATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.1 Choosing the emulated device: W7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Mask option on Port B: W3 and W4 for ST626X and ST629X . . . . . . . . . . . . . . . . 4.2.3 Hardware WATCHDOG selection: W1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 MIXT option: Wake UP by NMI in STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 Clock Source Selection: W2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.6 Reset delay duration: W5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 EMULATED PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Timer A, Timer 2, Watchdog . . . . . . . . . . 4.3.4 Analog to Digital Converter . . . . . . . . . . . 4.3.5 Serial Peripheral Interface (SPI) . . . . . . . 4.3.6 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9 Low Voltage Inhibit, Pin VCC (LVI) . . . . . 4.3.10 NMI/CKOUT . . . . . . . . . . . . . . . . . . . . . . ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... 15 16 16 16 17 17 18 18 18 18 18 18 19 19 20 20 20
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Table of Contents
5 TROUBLESHOOTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 - AT POWER UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 DURING EMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 DISCREPANCIES BETWEEN EMULATOR AND ROM OR EPROM DEVICE . . . . . . . . . 21 5.4 AVOID THE MOST FREQUENT PROBLEMS WHEN PROGRAMMING ST6 MICROS! . 22 5.4.1 Execution of Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Execution of WAIT and STOP instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ANNEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 COMPONENTS LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 23 23
6.2 ST626X-DBE SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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ST626X-EMU2 - DELIVERY CHECK
1 DELIVERY CHECK
This development tool is able to emulate all components belonging to the ST620X/1X/2X, ST625X/ 6X and to ST629X family. The dedication board is common for emulating the three families.Tthe choice of emulated ROM Device is made by properly setting the configuration on the dedication board, and connecting the appropriate PROBE on the appropriate connectors. The development tool is delivered with: - the ST6 mainframe emulator or the new ST6 HDS2 emulator - a 5 Volts power supply is added with the new ST6 HDS2 emulator - 2 flat cables for connecting one of the probes to the dedication board To emulate ST626X/9X families: - a 28 pin DIL emulation probe for ST625X/6X and ST629X (Ref. DB051 with DIL28 footprint). - a 20 pin DIL emulation probe for ST625X/6X and ST629X (Ref. DB051 with DIL20 footprint). To emulate ST620X/1X /2X families: - a 28 pin DIL emulation probe for ST620X/1X/2X (Ref. DB210 with DIL28 footprint). - a 20 pin DIL emulation probe for ST620/1X/2X (Ref. DB210 with DIL20 footprint). - a 16 pin DIL emulation probe for ST620X/1X/2X (Ref. DB210 with DIL16 footprint). Finally, a DIL footprint to SO footprint adapter is also included in the package: - DB090: a 28 pin DIL to 28 pin SO adapter - DB093/20: a 20 pin DIL to 20 pin SO adapter - DB093/1: a16 pin DIL to 16 pin SO adapter Instructions for use - Warning This development tool conforms with the EN55022 emissions standard for ITE, and with generic 50082-1 immunity standards. Then, it complies with the 89/336/EEC directive. The product is a A Class apparatus. In a residential environment this device may cause radioelectrical disturbance which may require that the user adopts appropriate precautions.
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ST626X-EMU2 - ST6 HDS2 NEW MAINFRAME EMULATOR
2 ST6 HDS2 NEW MAINFRAME EMULATOR
The new ST6 HDS2 mainframe has been designed to replace the old one. The main modifications are: - communication transfer rate: it is now much faster thanks to the use of parallel port. - dimension and weight: the old 3 boards, basic part of the system, have been redesigned in one board. - the cost of the overall system has been well reduced In the second version of ST6 HDS2, (metal box with MB174 main Board) modified for EMC conformity, new features have been introduced: - Read/Write registers on the fly during execution of program without any wait state. - Selective record of bus in logical analyseur in Range or Start/Stop mode. - Output OUT1 and OUT2 for synchronisation of an external equipment, programmable in the same way as Selective trace, in Range or Start/ Stop mode. Figure 1. Hardware Development System Emulator - Stack overflow: a break is automatically generated (by default) in case of stack overflow. - Break execution: in this new version, the program stops before the execution of the fetch. These new mainframes consist of a basic part, common to all ST6 devices, and one ST62 or ST63 sub family dedicated board depending on the specific device to emulate. This new emulator is fully compatible with existing dedicated boards, excepting ST638X and ST631XX which have been designed in 2 boards. Only the dedicated board (DBE) has to be changed to emulate a new device within the ST62/ ST63 sub families. The use of parallel port allows a very fast communication transfer rate. The symbolic debugger, software part of the real time emulation tool, can be run on a PC, and is common to all ST62 and ST63 devices. The debugger uses a windowed menu driven interface, and enables the user to set the configuration of the emulator.
HARDWARE DEVELOPMENT SYSTEM EMULATOR (HDS2)
Parallel Port connection
Dedication Board
Power
OUT-1 OUT-2
Stop Wait Run
4321
Triggers
ST6 HDS2 EMULATOR (.EMU2)
ST6 probe
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ST626X-EMU2 - ST6 HDS2 NEW MAINFRAME EMULATOR
2.1 MAIN BOARD The Main board controls the emulator thanks to a ST9 central processing unit which performs commands coming from host computer through the parallel line. The board contains, all emulation resources, the core of the ST6, Program ROM emulation, break point, trace memory, automaton and all necessary logic for a real time emulation. Two connectors, J1 and J2, are used to exchange signals with the interface board. The amount of program memory in the main board is factory set at 32k, in fact the size of the memory depends on the dedication board, which contains the Program Rom Pagination Register (PRPR) if it exists (no PRPR for memory size lower than 4k). No configuration jumpers are required. 2.2 ST6 HDS2 MAIN BOARD On the rear panel there is: - a power plug to connect power: 5 Volts 3 Amp min. (The delivered power is 100 volts to 240 volts input and 5 Amp output). - a power switch. - a parallel connector for an IBM PC(TM) compatible. On front panel: - a led "POWER ON" signal. - OUT 1 and OUT 2 signals which can be used for synchronizing an external equipment. - 3 leds indicating when the ST6 core is in "STOP", "WAIT" or "RUN" mode. - a 16 pin connector for data acquisition signals. The explanation of these signals is done in the debugger manual.
2.2.1 External output: OUT1 and OUT2 For debugging hardware it is very useful to have synchronization signals. The goal of the outputs 1 and 2 is to offer this feature to the user. They can be programmed differently whether the debugger used is the DOS debugger ST6NDB or the Source Level Debugger WGDB6, as explained in the two following paragraph. They are full programmable with WGDB6. Ouptput OUT1 and OUT2 under ST6NDB When using old DOS Version of debugger ST6NDB: This feature is programmable thanks to Hardware Breakpoint Menu. The breakpoint MENU allows to define breaking events. These events will generate an actual breakpoint only if break enable is ON. When break is off, these events are existing in the development tool. In the HDS2 emulator version up to 4.3, the signals OUT1 and OUT2 are connected to these internal breaking events. Therefore these signals can be used to synchronize an external device while running (breakpoint off). Ouptput OUT1 and OUT2 under WGDB6 When using WGDB6 new Version of debugger at source level under WindowsTM : This feature is full programmable thanks to Hardware Events/Trigger Menu. Output OUT1 and OUT2 can be programmed in two ways: - Events for synchronisation: it allows to the user to preset pulses synchronisation for an external equipment. The events can be defined by addresses or by range of addresses. - Events for Timing Measure: it allows to the user to measure time elapsed during a subroutine for example. In this case, output OUT2 is SET on a user defined address, and RESET on an other one, OUT1 is the ST6 clock cycle gated by OUT2. These 2 functioning modes are clearly displayed on screen.
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ST626X-EMU2 - ST6 HDS2 NEW MAINFRAME EMULATOR
2.2.2 Data acquisition signals In a same way as are recorded Buses, Flags, Bank registers in the trace memory, the ST6 HDS2 offers to the user the possibility to record 4 external signals. These signals must be connected on the pin of the Analyser probe connector on the front panel of the HDS2, as shown below. These inputs are CMOS compatible at 5 Volts. 2.2.3 LEDs RUN, STOP, WAIT Three leds have been added to indicate to the user the state of the core or of the development tool during emulation. When user's program is running (in real time), led RUN is on. When ST6 core is in WAIT mode, led WAIT is ON.
VCC Caution: +5V EMU
GND
1
AL3
AL2 AL1 AL0
When ST6 core is in STOP mode, both leds STOP and WAIT are ON.
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ST626X-EMU2 - ST6 HDS2 NEW MAINFRAME EMULATOR
2.3 INSTALLING THE PROBE: Before installing the probe, the user must choose the device to be emulated: ST620x/1x/2x or ST625x/6x or ST629x Then, - Connect the 2 flat cables on the appropriate connectors, if the board is inside the main frame, unscrew the 2 screws on each side of the dedication board, and press outward on the release buttons to extract the board. - The connectors are J1 and J2 for ST625X/6X and ST629X family (printed on board). - The connectors are J3 and J4 for ST620X/1X/2X family (printed on board). To prevent mistakes, a bump on connectors impose to set them right. Furthermore, we can verify that the pin 1 for each connector, which is clearly printed on both boards, is on the same side as the red line on the flat cables. Then connect the chosen probe on the opposite side of the flat cables, with respect to the pin 1 of each connector. Schematics of these probes are shown in annex. The ST620X/1X/2X probes emulate the oscillator function if the jumper on the probe is set on crystal. If set on OSCIN, a clock must be given on OSCIN input. To use this clock issued from probe, the dedication board must be set on external clock.
2.4 INSTALLING AN ST6 EMU2 DEVELOPMENT TOOL When receiving a whole development tool, the dedication board is delivered inside the mainframe. The user has just to: - connect the power supply to the mains(100 to 240 volts). - connect the output (5Volts) of power supply on the DIN connector of the rear panel - connect the parallel cable between the parallel connector and the host computer. 2.5 INSTALLING A ST626X-DBE DEDICATION BOARD IN AN ST6 HDS2 If there is already a dedication board in the development tool, the user has simply to: - unscrew the 2 screws on each side of the dedication board, and press outward on the release buttons to extract the board. Then insert the new dedication board in the guide rods and push it hardly in the backplane, and: - screw the 2 screws on each side of the dedication board.
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ST626X-EMU2 - ST6 HDS2 NEW MAINFRAME EMULATOR
2.6 COMPONENTS LAYOUT OF ST6 MAIN BOARD (MB097)
A1 902 R V
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ST626X-EMU2 - ST6 HDS2 NEW MAINFRAME EMULATOR
2.7 COMPONENTS LAYOUT OF ST6 MAIN BOARD (MB174)
VR02091U
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ST626X-EMU2 - ST6 MAINFRAME EMULATOR (FIRST GENERATION)
3 ST6 MAINFRAME EMULATOR (FIRST GENERATION)
The ST6 mainframe emulator contains positions for 5 boards: - Mother board (CLZ80) must be inserted on the first (bottom) position - Real time board (GPFM/3) must be on second position - interface N (DB014) must be inserted on third position - dedication board ST620X/1X/2X/5X/6X/9X-DBE (MB064) inserted in one of the two top position On the rear panel there is: - a main-power selector to select 110 volts or 220 volts. - a power plug - a power switch On front panel: - the RS232 connector to link the emulator with an IBM PC - EXT-SIG connector that allows you to choose between 3 groups of 4 signals to be memorize on trace memory. These signals are independent from the probe data acquisition signals. The explanation of these signals is done in the debugger manual - Mother board reset push button - ST6 INT push-button 3.1 MOTHER BOARD (CLZ80) The mother board (CLZ80) controls the mainframe emulator and it is linked to an IBM PC through an RS232 line. On this board only 2 connectors are used: - J5 connected to the front panel RS232 25 pin connector - J4 connected to the front panel mother board reset push-button 3.2 REAL TIME BOARD (GPFM/3) Real time board (GPFM/3) contains the emulation resources: - ROM Program emulation, break point, trace memory. - Two connectors, J3 and J4, are used to exchange signals with the interface board. When emulating ST62XX or ST63XX, the interface board is an N-WELL interface board. The two connectors are used. For emulating components of other families, the interface board can be a P-WELL interface board: in this case only one connector is used, the jumpers of W2 must be plugged. JUMPERS SETTING for ST62XX and ST63XX emulation: W1: All jumpers must be removed. W2: One jumper only must be set to link pin 1 to pin 16. CONNECTORS: J3 and J4: Used to link this board with the N-WELL interface board. J5: Used to connect the data acquisition probe.
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ST626X-EMU2 - ST6 MAINFRAME EMULATOR (FIRST GENERATION)
3.3 INTERFACE BOARD The interface board emulates the CPU-core. JUMPERS SETTINGS: S1: - not used in emulation mode - allows the definition of the type of EPROM (27256/27128) used in stand-alone (without CLZ80 and GPFM/3 boards) mode S2, S3: size of emulation program ROM The position reference names depend on the version of the board. For S2 they can be identified as 0 and 1 or OLD and NEW on the board. For S3 it can be 0 and 1 or 4K and 8K.
S2 0 or OLD 0 or OLD 1 or NEW 1 or NEW S3 0 or 4K 1 or 8K 0 or 4K 1 or 8K Size 4K 8K 16K 32K normal setting not supported Comment
3.4 ST626X-EMU DEVELOPMENT TOOL When receiving a whole development tool, the dedication board is delivered inside the mainframe, it is plugged in one of the two top position in the backplane. First of all, it is mandatory to verify the mainframe: - remove the 2 screws on the rear panel of the main frame - lift the lid on the side of the rear panel - pull the lid from the rear panel, it dissociates it from the front panel - remove the lid, pay attention to the wire for the ground connection Verify that all boards are correctly inserted in the backplane of the mainframe in the right order: - CLZ80 board must be inserted on the first (bottom) position - GPFM/3 board must be on second position - Interface N (DB014) must be inserted on third position - The two top positions are intended to receive one or a couple of dedication boards in order to emulate one family of component: in this case, only the ST626X-DBE board must be in one of the two top positions.
The purpose of this jumper is to allow the emulator to check the amount of emulation program ROM that is used. TEST/NO TEST: must be in NO TEST position CONNECTORS: J1 and J4 to link this board to GPFM/3 board. J2: receives signals from J1-EXT SIG. connector situated on the front panel of the ST6 emulator. J3: is connected to ST6-RESET, ST6-INT pushbuttons, STOP-LED and WAIT-LED situated on the front panel of the ST6 emulator.
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ST626X-EMU2 - ST6 MAINFRAME EMULATOR (FIRST GENERATION)
3.5 INSTALLING ST626X-DBE DEDICATION BOARD When receiving only a dedication board, the user must install his dedication board as described below. Open the main frame by removing the lid: - remove the 2 screws on the rear panel of the main frame - lift the lid on the side of the rear panel - pull the lid from the rear panel, it dissociates it from the front panel - remove the lid, pay attention to the wire for the ground connection Then remove the dedication board or the two dedication board which are plugged in the two top position of the backplane, which was for emulating an other family of STMicroelectronics devices. After that, plug the new dedication board in one of the two top positions of the backplane.
3.6 INSTALLING THE PROBE Before installing the probe, the user must choose the device to be emulated, please refer to 4.2.1 chapter. Then, - Connect the 2 flat cables on the appropriate connectors. The connectors are J1 and J2 for ST625X/6X and ST629X family (printed on board). The connectors are J3 and J4 for ST620X/1X/2X family (printed on board). To prevent mistakes, a bump on connectors impose to set them right. Furthermore, we can verify that the pin 1 for each connector, which is clearly printed on both boards, is on the same side as the red line on the flat cables. - Then, remove the 2 screws which are holding a small metal cover on the bottom of the development tool. - Stick the flat cables through this new opening. Then connect the chosen probe on the opposite side of the flat cables, with respect to the pin 1 of each connector.
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ST626X-EMU2 - DEDICATION BOARD (DBE)
4 DEDICATION BOARD (DBE)
This board contains the specific functions for ST620X/1X/2X, ST625X/6X and ST629X emulation : - Oscillator - EEPROM (Byte mode and parallel mode) - RAM - Timer A - Timer 2 - Watchdog - Analog to Digital Converter - Serial Peripheral Interface - Analog to Digital Converter - Port A: 8 Bits - Port B: 8 Bits - Port C: 8 Bits (one part for ST625X/6X, ST629X, the other for ST620X/1X/2X) - Low Voltage Inhibit - Pagination Registers A white dot indicates the position 1 for all jumpers and components on the board. Note for the VCC pin: When the input power pin VCC is connected, this input is used as a reference voltage by the emulator.(please refer to Figure 4.1 chapter) No power is given or taken at this pin by the emulator. Notes on write-only registers: Several Data Space registers of the emulated ROM device are write-only, however, to offer more flexibility to the user, they are readable when commands such as "watching register" are used. 4.1 VOLTAGE FUNCTIONING RANGE This board has been designed to emulate the ROM device in the range of 3 to 6 Volts. When the input power VCC pin is connected, this input is used as a reference voltage by the emulator. This reference voltage is buffered thanks to an operational amplifier and an emitter follower for powering the output buffers, and for giving the high reference voltage to the ADC. Then all the outputs of the peripherals are fully compatible at CMOS level with an application which is powered in the range from 3 to 6 Volts. When this input is not connected, all buffers are powered with 5 volts. No power is given nor taken at this pin by the emulator.
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ST626X-EMU2 - DEDICATION BOARD (DBE)
4.2 JUMPER DESCRIPTION ON DEDICATION BOARD Jumpers on the board are used to select the amount of MEMORY, the emulated PERIPHERALS, and metal MASK OPTION of the ROM device. This chapter explains how to select these features. Note for ST620X/1X/2X: The difference between ST620X/1X and ST622X is only about the size of ROM and A/D presence. As the Development Tool offers the maximum of ROM, the choice will be always a device of the ST622X family. 4.2.1 Choosing the emulated device: W7 This board has been designed to emulate 3 families of ST6 components: ST621X/2X, ST626X and ST629X. The choices are different whether ADC and SIO are used, or Pin 23 or Pin 17 respectively is NMI or CKOUT, or with the amount of DATA space memory. To select this choice, only one jumper must be set on W7 in front of the name of the name of the device, clearly printed on the board. When a peripheral is not used, for example SIO for ST6292, registers of this peripheral are at zero value, and they cannot be written.
Emulated Device Jumper on W7 NMI/CKOUT
4.2.1.1 Emulating ST621X/2X family: J3 and J4 To emulate a ROM device of the ST621X/2X family, a ST621X/2X probe must be connected on J3 and J4 through the flat cables. There is one probe for emulating 28 pins ROM devices (DB031), and one probe for emulating 20 pins ROM devices(DB030). J3 of the dedication board must be connected on J1 of the probe. J4 of the dedication board must be connected on J2 of the probe. The number of the pins are clearly printed on both boards, and the red line on the flat cables must be on the same side of the 1 of the connectors. 4.2.1.2 Emulating ST626X or ST629X family: J1 and J2 To emulate a ROM device of the ST629X or ST626X family, the corresponding probe must be connected from J1 and J2 of the dedication board to respectively J1 and J2 of the probe, through the flat cables. The 28 pins probe emulate 28 pins ROM devices, the 20 pins probe emulate 20 pins ROM devices. The following table shows the difference between emulating ST626X or emulating ST629X.
ADC/SIO SPI Data Space Memory 1 RAM Bank (0->3F) 2 EEPROM BANK (0->3F) EEPROM (0->2F) 1 RAM Bank (0->3F) 2 EEPROM BANK (0->3F) 1 RAM Bank (0->3F) 1 EEPROM BANK (0->3F) 1 RAM Bank (0->3F) 0 EEPROM BANK
ST6293/94
ST6293/94
CKOUT
YES
YES
ST6291/92
ST6291/92
CKOUT
NO
NO
ST6260/65
ST6260/65
NMI
YES
YES
ST6263*
ST620/65
NMI
YES
NO
ST6253*
ST6260/65
NMI
YES
NO
* Be careful not to try to emulate the SPI on ST6253/63 and also the EEPROM on ST6253 as those peripherals don't exist on these devices
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ST626X-EMU2 - DEDICATION BOARD (DBE)
4.2.2 Mask option on Port B: W3 and W4 for ST626X and ST629X There is two option bits for the state of the bit port PB0, PB1, PB2, PB3 during RESET. This state can be input with pull-up or high impedance. The option byte 4 is for both PB0 and PB1, the other, option Byte 5, is for PB2 and PB3. OPT4: Option Byte 4 When the jumper is between 1 and 2 the option is 0: Pull-up during reset for PB0 and PB1. When the jumper is between 2 and 3 the option is 1: high impedance during reset for PB0 and PB1. OPT5: Option Byte 5 When a jumper is between 1 and 2 the option is 0: Pull-up during reset for PB2 and PB3. When a jumper is between 2 and 3 the option is 1: high impedance during reset for PB2 and PB3. The factory setting for these jumpers is: Pull-up during reset. When emulating ST621X or ST622X these jumpers are ignored.
VR02091P
4.2.3 Hardware WATCHDOG selection: W1 The jumper W1 permits to emulate the "hardware WATCHDOG" metal mask option of the ROM device. The watchdog can be activated in two ways in the ROM device: - The software Watchdog is activated by setting, by software, bit 0 of the watchdog register. - The other way is to be in "watchdog HARD", it means the watchdog is automatically armed after RESET (generated by watchdog or not). Jumper setting: 1-2: Watchdog is automatically activated by HARDWARE 2-3: Watchdog is only activated by SOFTWARE The jumper setting is clearly printed on board as shown in the following figure 3. Note: When activating watchdog, STOP instructions are automatically executed as WAIT instructions by the processor, see following chapter for special use of STOP mode. 4.2.4 MIXT option: Wake UP by NMI in STOP mode A special option is to effectively execute STOP mode when encountered, and to wake up from this STOP mode by using NMI pin. This feature is only available when ST6223/24, or ST626X when MIXT option is selected. When this feature is selected, even if watchdog has been activated (Hard or soft), STOP instructions are effectively executed, when pin NMI is HIGH. If pin NMI goes low, or was low before executing STOP, STOP instructions are converted in WAIT instructions. Jumper setting W7: Two ways: - Select ST6223/24 clearly printed on board - Put a jumper between pin 3 and 4 pin of W7 and select ST6260/65 clearly printed on board.
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ST626X-EMU2 - DEDICATION BOARD (DBE)
4.2.5 Clock Source Selection: W2 The system CLOCK can be chosen between internal on board oscillator and pin OSCIN (or XTAL) input of the probe. This jumper setting is clearly printed on board, with INT for INTERNAL clock and EXT for EXTERNAL clock. Jumper setting: 1-2 In this case the external clock is selected: it means the Clock issued from the probe is selected. 2-3 The internal clock is selected. In this case the internal clock is made thanks to an oscillator with a quartz, this quartz XT1, can be exchanged if desired by the user.
For delay of 4096, 8192 or 16384 the jumper must be in front of respectively 4, 8, or 16, clearly printed on the board.
VR02091Q
VR02091Q
4.2.6 Reset delay duration: W5 For as long as the reset pin is kept at the low level, the processor remains in the reset state. After the pin reset has been released, a counter provides a delay between the detection of the reset high level and the release of the MCU reset: a jumper on W5 permits to select the duration of this delay. The standard delay is 2048 oscillator cycles: the jumper must be in front of 2.
Note for CLOCK "issued from the probe": If the user uses a probe made by STMicroelectronics, this probe is able to send a clock to the dedication board in two ways thanks to a jumper: - a clock made by the on board oscillator on the probe. - a clock directly issued from the application. In this case the signal on OSCIN must be at CMOS level. When oscillator is not used, it is mandatory to disable the oscillator by putting a jumper on "oscillator disable" (factory setting). WARNING on probe on board oscillator: Probe: The "open" schematic of this probe permits to the user to reconstruct on the probe, the same oscillator as on his own application. The probe is able to support a cristal or a resonator 3 pins with or without capacitor, it can be of course used also with an RC. PROBE: Installing the ferrite coil for EMC compatibility To be conform to the EMC directive, particularly in emission, the delivered ferrite coil must be placed as follow: 1) Place each part on each side of the flat cables 2) Place the metal clip to fix them together
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ST626X-EMU2 - DEDICATION BOARD (DBE)
4.3 EMULATED PERIPHERALS 4.3.1 Oscillator For the ST621X/2X it is a standard oscillator as described in the data sheet of the ROM device. For ST626X and ST629X, the four bits of the oscillator control write only register 0DCH are emulated, including RC oscillator frequency control (if Bit2=1 then Fosc is approximately divided by 100), but the pin XTAL and EXTAL are respectively input and output clock for the emulator, according to W2 selector. These two pin XTAL and EXTAL do not emulate an actual oscillator, on which it can be connected a crystal or an RC. 4.3.2 Mapping Program memory size is always valid up to 4 k Bytes (0FFFH) Data space memory size depends on the emulated device. The mapping of data space can be different in two ways: there is bank memory in the range 0 to 03FH or not. - No Memory Banks: case of ST6291, ST6292. - In this case, there is always EEPROM from 0 to 02FH, and nothing from 30 to 3F. - The Memory Bank Register (0E8H), is at 0 value, and it is not possible to write it. - Memory Banks exist: case of ST6293, ST6294, ST626X. - In this case the range from 0 to 03FH is fully used through the content of the Memory Bank Register located in 0E8H (write only). The meaning of each one of these bits is: Bit 0 if set selects the first EEPROM bank Bit 1 if set selects the second EEPROM bank Bit 4 if set selects the RAM bank. The others are not used and not existing. Care must be taken that only one of these three bit must be set at a time, for more details see Data Sheet of the corresponding ROM device. 4.3.3 Timer A, Timer 2, Watchdog Clock of these devices are voluntarily validated only during emulation, it provides to see the evolving values of them. Therefore pay attention that in NEXT mode the values of counters can be slightly different of a real time session because of setting ON and OFF emulation. For using these peripherals, please, refer to data sheet of the corresponding ROM DEVICE. 4.3.4 Analog to Digital Converter This peripheral is available only when one component of ST620X/1X/2X, ST629X or ST625X/6X family, which contains ADC, has been selected with W7 jumper. Except these devices, ADC registers are at zero value and are not able to be written. The ADC input can be connected at one of the 13 inputs, the 8 of port A and the 5 of port C, by properly programming the registers of these ports (one at a time). If more than one ADC input are selected, they will be short circuited each other's. The analog to Digital Converter converts the input value in about 50S at 8 Mhz of Xtal clock. Clock conversion is always present, it means that a data conversion is always accomplished after writing a start conversion even if it is made in NEXT mode of emulation. It allows to the user to convert analog input step by step. Note on ADC voltage reference: The high voltage reference for the ADC is the applied voltage on the pin VCC internally buffered in the board. The low voltage reference is the GROUND. Then to have a conversion result of 0FFH, the voltage at the analog input must be equal to the voltage of the VCC pin. 4.3.5 Serial Peripheral Interface (SPI) This peripheral is available only when one of ST6293, ST6294 or ST626X has been selected with W7. For other devices, SPI registers are at zero value and are not able to be written. The Serial Peripheral Interface, when validated, is always active: it means clock and data do not depend whether on the system is in step by step mode or not. For using this peripheral, please, refer to Data Sheet of the corresponding ROM device. Note: to use this peripheral, do not forget to set bit 1 of LVI register...
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ST626X-EMU2 - DEDICATION BOARD (DBE)
4.3.6 Port A This port is always selected whatever is the emulated device, and if ADC is permitted (see 3.3.4 chapter), each input of this port can be an ADC input (one at a time). The functioning mode of each 8 input is selected by properly programming the three associated registers: Data Register (DRA), Data Direction Register (DDRA), and Option Register (ORA) as follow.
DDR OPR DR I/O Mode Input without pullup, interrupt disabled Input with pullup, interrupt enabled Input with pullup, interrupt disabled Analog Input
For more details about this peripheral, please, refer to Data Sheet of the corresponding ROM Device. 4.3.7 Port B This port is always selected, the functioning mode of his 8 input is selected by properly programming the three associated registers: Data Register (DRB), Data Direction Register (DDRB), and Option Register (ORB) as follow.
DDR OPR DR I/O Mode Input without pullup, interrupt disabled Input with pullup, interrupt enabled Input with pullup, interrupt disabled Push Pull Output Open Drain NMOS output
0 0 0 1
X 1 0 1 0
1 0 0 X X
0 0 0 0 1 1
0 1 0 1 1 0
1 0 0 1 X X
1 Push Pull Output Open Drain NMOS output
Beware of mixing input and output modes in the same port, in this case, do not use SET or RES instructions on Data Registers: When a port bit is in input mode, the data read is the state of the pin of the device (or the probe); when a port bit is in output mode the data read is the data register, so when using a read/modify/ write instruction, a bit port mode can be changed from input mode to analog input mode unintentionally!
Beware of mixing input and output modes in the same port, in this case do not use SET or RES instructions on Data Registers: When a port bit is in input mode, the data read is the state of the pin of the device (or the probe); when a port bit is in output mode the data read is the data register, so when using a read/modify/ write instruction, a bit port mode can be changed from input mode to analog input mode unintentionally!. For more details about this peripheral, please, refer to Data Sheet of the corresponding ROM Device.
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ST626X-EMU2 - DEDICATION BOARD (DBE)
4.3.8 Port C This port is always selected, and if ADC is permitted (see 3.3.4 chapter), each input of this 8 bit port can be an ADC input (one at a time). The functioning mode of each 8 input is selected by properly programming the three associated registers: Data Register (DRC), Data Direction Register (DDRC), and Option Register (ORC) as follow. Bit PC0 to PC4 are used for ST626X/9X, PC4 to PC7 are used for ST621X emulation.
DDR OPR DR I/O Mode Input without pullup, interrupt disabled Input with pullup, interrupt enabled Input with pullup, interrupt disabled Analog Input Push Pull Output Open Drain NMOS output
0 0 0 0 1 1
0 1 0 1 1 0
1 0 0 1 X X
Beware of mixing input and output modes in the same port, in this case, do not use SET or RES instructions on Data Registers: When a port bit is in input mode, the data read is the state of the pin of the device (or the probe); when a port bit is in output mode the data read is the data register, so when using a read/modify/ write instruction, a bit port mode can be changed
from input mode to analog input mode unintentionally! For more details about this peripheral, please, refer to Data Sheet of the corresponding ROM Device. 4.3.9 Low Voltage Inhibit, Pin VCC (LVI) Pin VCC on probe is an input for LVI system, and do not furnish any power to the application. A low Voltage inhibit system permanently watches Pin VCC on the probe. It generates a RESET when pin VCC goes under 2.5 Volts threshold and releases it when it goes over 3 Volts, at the same time bit 7 of LVI register (0DDH) is set to one. For more details about this peripheral, please, refer to Data Sheet of the corresponding ROM Device. 4.3.10 NMI/CKOUT The NMI/CKOUT PIN, pin 23 for 28 Pin package, pin 17 for the 20 pin package, can be either NMI entry or CKOUT output depending on the selected device (see 3.3.1 chapter). It is NMI input for ST626X family, and CKOUT for ST629X. When NMI is selected, the pin is the Non Maskable interrupt input for UC. When CKOUT is selected, the pin is an output clock whose the frequency is clock on XTAL divided by 2. CKOUT output is controlled by bit 3 of Oscillator Control Register (0DCH): If bit 3 is set: CKOUT is low If bit 3 is reset: CKOUT = Fosc/2 For more details about this peripheral, please, refer to Data Sheet of the ROM Device.
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ST626X-EMU2 - TROUBLESHOOTING
5 TROUBLESHOOTING
5.1 - AT POWER UP At the beginning of an emulation session, on screen of PC must appear the debugger message, with "WAIT" during software connection establishment. If a "TIMEOUT" message is encountered, there is a connection problem, which can come from one of these reasons: s when using ST6HDS2 - ST6 development Tool is not power ON - The parallel line is not well connected s or when using old main frame: - verify that the delivered cable is actually connected directly to the Main Frame. - and if necessary there is another cable which is either a "wire to wire" connection or a 25 to 9 pin adaptor. - The serial line is not connected to the right I/O port of the computer. 5.2 DURING EMULATION During emulation: Problem with program Counter In case of "Check Hardware Jumpering" or wrongly executing code in step mode: Most of the time, this problem occurs with HDS1 emulator or with HDS2 plastic BOX up to 4.3 version, it is coming from that the development tool is in RESET state, it can be caused by: - The application where probe is connected is not powered on, then the schmitt trigger on pin Reset is active and causes the RESET - The pin Reset of emulated device is at low level - A probe is connected, but is not powered either by an application or by a voltage on the VCC input. For properly emulating RESET please refer to the following chapter. During emulation: Reset emulation With ST6HDS2 new metal box, it is now possible to begin an emulation session even if application is off, it is required particularly in MONITOR or TV applications. With old ST6 HDS1 emulator, or with HDS2 plastic BOX up to 4.3 Version, if the application requires that software must be executed just after power ON, it is mandatory to proceed as follow: - not connect, or remove probe from application. - power ON emulator. - begin emulation session: load program. - then start execution of program in Real Time. - plug the probe in the application (which is off), at this time the ST6 emulator is in reset state, because Reset and VCC pins are at low level. - Power ON the application, then the execution of software will start. 5.3 DISCREPANCIES BETWEEN EMULATOR AND ROM OR EPROM DEVICE When some differences of behaviour are appearing between the emulator and the ROM device, in most cases, it comes from using read/modify/ write instructions on: - registers which are only writable. - registers in which some bits are writable, and some bits readable. For these registers, trouble are caused, because when reading, a random value is read by the CPU, after calculating the mask, this random value is written in the register, changing it unintentionally! The same problem can occur with registers, where some bits have a different function during writing or during reading. Example for Ports: When reading a bit port in input mode, the read value is the level of the pin. When reading a bit port in output, the read value is the value of the corresponding bit in the Data Register. The user has to check if each used register is correctly accessed. The principle ST6 registers, with which care must be taken, are listed below: - The EEPROM control registers - The control registers of SPIs - The Data registers of the 3 Ports A, B and C - Analog to Digital Converter Control Register - The Interrupt Option Register - The Program Rom Pagination Registers - The Data RAM/EEPROM Banking Register - The Data ROM window Register
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ST626X-EMU2 - TROUBLESHOOTING
5.4 AVOID THE MOST FREQUENT PROBLEMS WHEN PROGRAMMING ST6 MICROS! 5.4.1 Execution of Interrupt If interrupt are not executed, in most cases, it comes from: - The core is not in normal mode: after RESET the core is in NMI mode, to enter the normal mode which let execute interrupt, the core must execute a RETI instruction. - The global enable interrupt bit has not been SET, or has been unintentionally cleared, then the IOR register must be checked. The default value to enable Interrupts is 010H. - The enable interrupt bit of the desired peripheral has not been SET, or has been unintentionally cleared. - The Interrupt Option Register is write only, and has been wrongly written by a read/modify/write instruction, only LDI is permitted. 5.4.2 Execution of WAIT and STOP instructions In WAIT mode, led WAIT is ON, in STOP mode the 2 led WAIT and STOP are ON (on the front panel of the emulator). If STOP or WAIT instructions are not exited, it comes from: - The core is not in normal mode: after RESET the core is in NMI mode, to enter the normal mode which let execute interrupt to exit from these states, the core must execute a RETI instruction.
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ST626X-EMU2 - ANNEX
6 ANNEX
6.1 COMPONENTS LAYOUT
VR02091O
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ST626X-EMU2 - ANNEX
6.2 ST626X-DBE SCHEMATICS Figure 1. Main sheet
VCC -12V P1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VME64 I GND VSS C7 47uF C2 47uF C1 470uF-EA C4 47uF C3 47uF VCC VDD VCC TP18 A[0..7] TY2 TY2 CYC01 CYC05 A1 A3 A5 A7 INTFLL PRUN0 INT0 INT2 INT4 INTRES WEA12 EXTINT CYC0I BDIO RESSO STOP INTFLL WRITE PRUN0 INT0 INT2 INT4 INTRES CLOCK CYCOI READ READ WRITE ROMADR CLOCK WEA12 INTRES PRUN EXTINT BDIO RESSO STOP WAIT STOP CLKSYST CK/12 VCE VCE VDDI VDDI IR RUN WT S K CK/12 1 TP1 5 I R W TP2 TP3 TP4
-12V +12V TY7 TY9
A0 A2 A4 A6 INTFR WAIT CYC01 INT1 INT3 EXTRES
TY9
INTFR WAIT +12V CYC01 CYC03 INT1 INT3 EXTRES
CYC05 PININT0
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
A[0..7]
TP5 ROMADRTP6 CK TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16
TP17 GND
RBB[0..3] J
RBB[0..3] RBB[0..3]
RBB0 RBB2
EXWR EXWR DRBB0 DRBB2 DRBB4 CLKSYST DRBB6 DRBB8 DD0 DD2 DD4 DD6 RAMPB0 RAMPB2 RAMPB4 RAMPB6
P2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VME64
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96
RBB1 RBB3 RESTO BIT4
RESTO
BIT4 ROMADR ROMADR DRBB1 DRBB[0..7] DRBB3 DRBB5
DRBB7 DD1 DD3 DD5 DD7 RAMPB1 RAMPB3 RAMPB5 RAMPB7
DD[0..7]
DD[0..7]
INTRES
RAMPB[0..7]
RAMPB[0..7] DRBB[0..7]
VR02091M
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ST626X-EMU2 - ANNEX
Figure 1. Main sheet (Cont'd)
PORTA, Timer 1
File : PATIM1.SCH PLD1A[0..4] DD[0..7] WRITE READ TY9 CLOCK NRESETI PRUN PULS PULS PLD1A[0..4] D[0..7] WRITE READ TY9 CLOCK NRESETI PRUN PULS TIM1IN TOUT TIMOUT NITTIM1 LATCH0 LATCH1 EXT[0..10] PA[0..7] PACAD[0..7] File : PORTB1.SCH PLD1A[0..4] DD[0..7] WRITE READ TY9B CLOCK EOCADC NRESETI PRUN LATCH0 LATCH1 PLD1A[0..4] D[0..7] WRITE READ TY9B CLOCK EOCADC NRESETI PRUN LATCH0 LATCH1 TIM1IN TOUT TIMOUT NITTIM1 LATCH0 LATCH1 EXT[0..10] PA[0..7] PACAD[0..7] EXT5 VCE VDDI PRUN VCC A0 A1 A2 A3 A4 A5 A6 A7 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 READ WRITE EXT1
PORTB, TIM2, RTC, IOR, CAD control
NITPB ITRTC NITTIM2 NADCRRR NITADC NSTARTADC PB[0..7] PBCAD[0..7] EXT[0..10] BIT4 INTFR INTFLL ADCCLOCK TEST NITPB ITRTC NITTIM2 NADCRRR NITADC NSTARTADC PB[0..7] PBCAD[0..7] EXT[0..10] BIT4 INTFR INTFLL ADCCLOCK TEST
PORTC, SI4, LVI
PLD1A[0..4] PLD1A[0..4] DD[0..7] WRITE READ CLOCK LATCH0 LATCH1 NRESETI PRUN PLD1A[0..4] D[0..7] WRITE READ CLOCK LATCH0 LATCH1 NRESETI PRUN File : PCSI4.SCH TIMOUT TOUT ITSI4 TIM1IN TIMOUT TOUT ITSI4 TIM1IN PC[0..7] PCCAD[0..7]
J5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 MW2X30C
EXT4 CLOCK
EXT6 GND EXT2 EXT3 EXT8 EXT7 EXT10 EXT9
EXT0
LATCH0 LATCH1
PC[0..7] PCCAD[0..7] EXT[0..10] RBB[0..3] LVI
PROBE Connection EXT[0..10] RBB[0..3] LVI PA[0..7] PB[0..7] PC[0..7]
CONTROL, ADRESS DECODING, INTERFACE POWER
File : CONTROL.SCH INT[0..4] CLOCK RESSO RESTO A[0..7] NITPB PRUN BDIO EXWR TY9B LVI VCKOUT ITSI4 NITTIM1 NITADC NITTIM2 ITRTC INT[0..4] CLOCK RESSO RESTO A[0..7] NITPB PRUN BDIO EXWR TY9B LVI VCKOUT ITSI4 NITTIM1 NITADC NITTIM2 ITRTC NRESETI RSTINT PLD1A[0..4] NRESETAP EXTRES VCCAPP READ WRITE EXTRES NRESETI RSTINT PLD1A[0..4]
EXTAL XTAL
EXTAL XTAL NRES CKNMI VSREF VCCAPP
CKNMI VSREF
READ WRITE
VCKOUT CKNMI OPTSER
VCKOUT CKNMI OPTSER
BANK, Clock Generation, Reset, WATCHDOG, Pag. Register
DD[0..7] WRITE READ NRESETI STOP WAIT TY9 PULS A[0..7] INTRES OPTSER TY2 RSTINT D[0..7] WRITE READ NRESETI STOP WAIT TY9 PULS A[0..7] INTRES OPTSER TY2 RSTINT File : EEPRBNK.SCH CLOCK CLKSYST PRUN PRUN0 EXTINT CKNMI VCKOUT EXT[0..10] TY2B TY9B RAMPB[0..7] DRBB[0..7] ROMADR OSCIN OSCOUT CLOCK CLKSYST PRUN PRUN0 EXTINT CKNMI VCKOUT EXT[0..10] TY2B TY9B RAMPB[0..7] DRBB[0..7] ROMADR XTAL EXTAL
CKNMI VCKOUT EXT[0..8]
Analog to Digital Converter
DD[0..7] FILE: CAD.SCH D[0..7] PA[0..7] PACAD[0..7] PB[0..7] PBCAD[0..7] ADCCLOCK NADCRRR NSTARTADC PC[0..7] PCCAD[0..7] EOCADC VSREF PA[0..7] PACAD[0..7] PB[0..7] PBCAD[0..7] PC[0..7] PCCAD[0..7] EOCADC VSREF VR02091N
ADCCLOCK
NADCRRR NSTARTADC
NADCRRR NSTARTADC
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30
RP8 1 File : PA07.SCH PUPPA[0..7] PUPPA[0..7] OUTPA[0..7] VOUTPA[0..7] INPA[0..7] PA[0..7] PA[0..7] PA[0..7] OUTPA[0..7] VOUTPA[0..7] INPA[0..7] 10K-S10 TOUT TIMOUT TOUT TIMOUT PORT A VCE VCE 1 VOUTPA7 VOUTPA6 VOUTPA5 VOUTPA4 VOUTPA0 VOUTPA3 VOUTPA2 VOUTPA1 2 3 4 5 6 7 8 9 10
PLD 1A0 PLD 1A1 PLD 1A2 PLD 1A3
26/38
333366 12245668 IC10 R9 PA2 470K EXT0 EXT1 EXT[0..8] PORTA OPTION RS5A 1 2 3 RS4B 3 2 4 1K-4R8P RS5B 4 5 RS4A 1 6 1K-4R8P 1 234567890 RS5C 6 7 RS4C 5 8 EXT[0..8] 65 64 63 62 61 60 59 58 D7 PLD1A4 LATCH0 INPA7 VOUTPA7 OUTPA7 PAUP/CAD7 D6 INPA6 VOUTPA6 OUTPA6 PAUP/CAD6 D5 INPA5 VOUTPA5 OUTPA5 PAUP/CAD5 57 56 55 53 52 51 49 48 47 46
RP4
RP13
VCE
PAUP/CAD0 PAUP/CAD7 PAUP/CAD1 PAUP/CAD2 PAUP/CAD6 PAUP/CAD5 PAUP/CAD3 PAUP/CAD4 LATCH0
2 3 4 5 6 7 8 9 10
1
LATCH1 OUTPA0 OUTPA1 OUTPA2 OUTPA3 OUTPA4 OUTPA5 OUTPA6 OUTPA7
10 9 8 7 6 5 4 3 2
10K-S10
10K-S10
PLD1A[0..4]
PLD1A[0..4]
ST626X-EMU2 - ANNEX
WRITE READ NRESETI CLOCK
NRESETI
Figure 2. Port A and Timer 1
D[0..7]
D[0..7]
PAUP/CAD0 OUTPA0 VOUTPA0 INPA0
Input Input Input Input Input Input Input Input/CLK
LATCH1 D0 12 13 14 15 17 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
4 5 6 7 8 9 10 11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O EPM5128 GND 10K-S10 1 VCC RP18 I/O I/O I/O I/O I/O I/O I/O I/O
PAUP/CAD1 OUTPA1 VOUTPA1 INPA1 D1 18 19 21 22 23
PAUP/CAD2 OUTPA2 VOUTPA2 INPA2 D2
RS5D 8 RS4D 7
W11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MW2X8C
OUTPA0 OUTPA1 OUTPA2 OUTPA3 OUTPA4 OUTPA5 OUTPA6 OUTPA7
22222233 45678901 P OV I A UON UT UP PPTA / AP3 C3 A A3 D 3 D 3 P OV I T A U ONY UT UP9 PPTA / AP4 C4 A A4 D 4 D 4 CK/12
33444444 89012345
NITTIM1 PULS
PRUN
PRUN
3 4 7 8 13 14 17 18 LATCH0 1 11
IC49 D0 D1 D2 D3 D4 D5 D6 D7 OC CLK 374E
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
PUPPA0 PUPPA1 PUPPA2 PUPPA3 PUPPA4 PUPPA5 PUPPA6 PUPPA7
PACAD[0..7]
LATCH0 LATCH1 PACAD[0..7]
TIM1IN
TY9
PAUP/CAD0 PAUP/CAD1 PAUP/CAD2 PAUP/CAD3 PAUP/CAD4 PAUP/CAD5 PAUP/CAD6 PAUP/CAD7 LATCH1
3 4 7 8 13 14 17 18 1 11
IC54 D0 D1 D2 D3 D4 D5 D6 D7 OC CLK 374E GND
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
PACAD0 PACAD1 PACAD2 PACAD3 PACAD4 PACAD5 PACAD6 PACAD7
VR02091J
PUPPA[0..7] VOUTPA[0..7] VOUTPA[0..7] OUTPA[0..7] PA[0..7] PA[0..7] INPA[0..7] PUPPA4 1 3 1 RS8A 100K-4R8P 1 2 IC41A 74HC126E 2 74HC14E 1 IC32A 3 2 PA4 IC53A 74HC126E PA0 OUTPA4 IC24A 3 INPA4 2 74HC4049I VOUTPA4 RS7A 100K-4R8P 2 1 IC48A 74HC126E IC33A 2 74HC14E 1 VCE 2 3 1 2
PUPPA[0..7]
OUTPA[0..7] INPA[0..7]
PUPPA0
VCE
VOUTPA0
1
Figure 3. Port A buffers
2
3
OUTPA0 IC25A 3 INPA0 2
IC42A 74HC126E
74HC4049I
PUPPA1 1 3 VCE 12 11 IC48D 74HC126E 1 3 OUTPA5 12 11 IC32F 12 13 74HC14E 4 6 IC48B 74HC126E 6 IC33B 4 74HC14E 3 INPA6 4 6 PA2 OUTPA6 IC24B 5 74HC4049I PUPPA7 1 0 VCE 9 IC48C 74HC126E 8 IC33E 10 11 74HC14E 8 PA3 7 RS8D 100K-4R8P 8 VOUTPA7 1 0 OUTPA7 INPA7 IC24E 12 11 74HC4049I 9 8 IC32E IC41C 74HC126E 10 11 74HC14E VCE 9 1 0 8 IC53C 74HC126E 5 RS8C 100K-4R8P VOUTPA6 4 5 6 IC41B 74HC126E IC32B 4 3 74HC14E VCE 5 6 IC53B 74HC126E IC41D 74HC126E 14 INPA5 15 74HC4049I PUPPA6 IC24F 11 IC33F 12 13 74HC14E 4 VCE 5 4 PA1 3 RS8B 100K-4R8P VOUTPA5 12 VCE 11 IC53D 74HC126E 1 3
PUPPA5
VOUTPA1
1 3
3 RS7B 100K-4R8P 4 PA5
OUTPA1
12
IC25F
INPA1
15
14
IC42D 74HC126E
74HC4049I PUPPA2
VOUTPA2
4
5 RS7C 100K-4R8P 6 PA6
OUTPA2
5
IC25B
INPA2
4
5
IC42B 74HC126E
74HC4049I
PUPPA3
VOUTPA3
1 0
7 RS7D 100K-4R8P 8 PA7
OUTPA3
9
IC25E
INPA3
12
11
IC42C 74HC126E
74HC4049I
VR02091K
ST626X-EMU2 - ANNEX
27/38
31
32
VCE 1 RP6 VCE 11 12 10K-S10 10K-S10 10K-S10 PULLUP on EPLD I/O : LOW = LOW , HIGH LEVEL = H Impedence RP2 VCE RP16 2 1 1 PBUPCAD7 2 OUTPB0 3 OUTPB7 PBUPCAD6 3 4 PBUPCAD5 4 OUTPB1 5 PBUPCAD4 5 OUTPB2 6 PBUPCAD3 6 OUTPB6 7 OUTPB5 PBUPCAD2 7 8 OUTPB3 PBUPCAD1 8 9 OUTPB4 PBUPCAD0 9 10 10 TS6 TS7 TS4 TS5 TS0 TS1 TS2 TS3 2 3 4 5 6 7 8 9 10 7 5 4 6 14 13 15 1 2 3 9 10 PO PO 74HC4060 R6 GND 470K PBUPCAD[0..7] PBUPCAD[0..7] PORT B File : PB07.SCH EXT2 PUPPB[0..7] PUPPB[0..7] OUTPB[0..7] VOUTPB[0..7] INPB[0..7] PB[0..7] PB[0..7] PB[0..7] OUTPB[0..7] TS[0..7] INPB[0..7] PBUPCAD[0..7] PBCAD[0..7] I I OOP OT D NNP P B US 0 P PT T UT 0 BB5 4 PP 10 CB A0 D 0 DT OP 7 SUB 7TU PP BC 7A D 7 GND 1 11 OC CLK 374E OC CLK 374E PBCAD[0..7] 1 11 XT1 QZ 32.768 R7 100K PBUPCAD0 PBUPCAD1 PBUPCAD2 PBUPCAD3 PBUPCAD4 PBUPCAD5 PBUPCAD6 PBUPCAD7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 3 4 7 8 13 14 17 18 PUPPB0 PUPPB1 PUPPB2 PUPPB3 PUPPB4 PUPPB5 PUPPB6 PUPPB7 PBUPCAD0 PBUPCAD1 PBUPCAD2 PBUPCAD3 PBUPCAD4 PBUPCAD5 PBUPCAD6 PBUPCAD7 IC39 D0 D1 D2 D3 D4 D5 D6 D7 2 5 6 9 12 15 16 19 3 4 7 8 13 14 17 18 2 5 6 9 12 15 16 19 IC22 D0 D1 D2 D3 D4 D5 D6 D7 PBCAD0 PBCAD1 PBCAD2 PBCAD3 PBCAD4 PBCAD5 PBCAD6 PBCAD7 IC13 Q4 PI Q5 Q6 RST Q7 Q8 Q9 Q10 Q12 Q13 Q14 11 10987654 IC8 IIIIIIII //////// OO OOOOO O I/O I/O I/O I/O I/O I/O I/O I/O 74 73 72 71 70 69 68 67 ITRTC INTEFR D6 TS6 OUTPB6 PBUPCAD6 EXT3 PRUN IIIIII ////// OOOOOO ADCCLOCK ITRTC IIII NNNN PPPP UUUU TTTT / C L K 88 2143 877777 098765 RS12A 1K-4R8P 2 RS12B 3 4 5 RS11A 2 3 RS11B 4 I/O I/O I/O I/O 65 64 63 62 INPB7 INPB6 INPB5 INPB4 RS12C 6 7 5 RS11C 6 7 RS12D 8 RS11D 8 1K-4R8P GND RP17 10K-S10 1 IIIIIIII //////// OOOOOOOO 44445555 67890123 N B E E P OT D I I XXB US4 T TTTUT4 T354PP I CB A4 M D 2 4 EPM5192 VCC TEST NITTIM2 BIT4 INTFR INTFLL EXT[0..8] EXT[0..8] I/O I/O I/O I/O I/O I/O IIIIII ////// OO OOOO 333333 345678 OP T T NE UBEYAX T US 9 DT P PT BC6 BC R 3A R R D 3 PPPP LLLL DDDD 1111 AAAA 0123 4444 1234 IIII NNNN PPPP UUUU TTTT 59 58 57 56 55 54 INPB3 INPB2 D5 TS5 OUTPB5 PBUPCAD5 PORTB OPTION OPEN : OPEN DRAIN OPTION CLOSED : PUSH-PULL OPTION W10 1 2 1 3 4 5 6 7 8 9 1 10 11 12 13 14 15 16 MW2X8C 1 234567890 OUTPB0 OUTPB1 OUTPB2 OUTPB3 OUTPB4 OUTPB5 OUTPB6 OUTPB7 NADCRRR NITADC NSTARTADC NITPB VR02091F GND
28/38
LATCH0 LATCH1
PRUN READ WRITE
D[0..7]
D[0..7]
CLOCK NRESETI
VCC
1
RP13 10K-S10
OPT4
234567891 0
ST626X-EMU2 - ANNEX
Figure 4. Port B and Timer 2
PULLUP HZ
W12 1 2 3 MW1X3C
PULLUP HZ
W11 1 2 3 MW1X3C OPT5
1 234567890
1
RP14 10K-S10
GND
PLD1A[0..4]
D1 TS1 OUTPB1 PBUPCAD1 INTEFLL NITADC
12 13 14 15 16 17
I/O I/O I/O I/O I/O I/O
EOCADC
NSTARTADC STARTRTC NITPB EOCADC
20 21 22 23
I/O I/O I/O I/O
PLD1A4 CLOCK2Hz D2 TS2 OUTPB2 PBUPCAD2 D3 TS3
25 26 27 28 29 30 31 32
I/O I/O I/O I/O I/O I/O I/O I/O
PLD1A[0..4]
TY9B
W9 1 2 MW1X2C
PUPPB[0..7] PB[0..7] PUPPB4 1 VCE INPB[0..7] 1 1 3 2 7 74HC4049I 5 74HC14E PUPPB5 1 3 12 11 IC40D 74HC126E 1 3 12 11 IC46D 74HC126E IC38D 8 9 74HC14E 4 PB1 IC33D 8 74HC14E PUPPB6 4 5 IC40B 74HC126E 6 PB2 OUTPB6 IC16C INPB6 6 7 74HC4049I PUPPB7 1 0 9 IC40C 74HC126E 8 PB3 IC32D 8 74HC14E 9 7 RS17D 100K-4R8P 8 VCE VOUTPB7 1 0 9 OUTPB7 IC16D INPB7 10 9 74HC4049I 8 IC46C 74HC126E IC21D 8 9 74HC14E VR02091B 9 1 0 8 IC45C 74HC126E 1 RS18A 100K-4R8P 2 PB7 IC32C 6 74HC14E 5 5 RS17C 100K-4R8P VOUTPB6 4 5 6 IC46B 74HC126E IC21C 6 5 74HC14E 6 VCE 5 4 6 IC45B 74HC126E 74HC4049I 9 3 RS17B 100K-4R8P VOUTPB5 VCE 12 11 IC45D 74HC126E 1 3 5 RS18C 100K-4R8P 6 PB5 74HC14E IC46A 74HC126E 6 5 IC38C PB4 IC40A 74HC126E 2 PB0 INPB4 6 IC33C 6 1 RS17A 100K-4R8P OUTPB4 IC29C 3 8 2 IC45A 74HC126E VOUTPB4 7 RS18D 100K-4R8P 2 3 PB[0..7] VOUTPB[0..7] OUTPB[0..7] INPB[0..7] PUPPB[0..7] VOUTPB[0..7] OUTPB[0..7]
PUPPB0
VOUTPB0
VCE
1
OUTPB0
2
3
IC25C
INPB0 6
7
IC23A 74HC126E
74HC4049I PUPPB1
Figure 5. Port B and Timer 2 buffer
VOUTPB1
VCE
1 3
OUTPB1
12 OUTPB5 IC29D 9 INPB5 10
11
IC25D
INPB1 10
9
IC23D 74HC126E
PUPPB2
74HC4049I
VOUTPB2
VCE
4
OUTPB2
3 RS18B 100K-4R8P 4 PB6
5
6
IC24C
INPB2 6
7
IC23B 74HC126E
74HC4049I
PUPPB3
VOUTPB3
VCE
1 0
OUTPB3
9
8
IC24D
INPB3 10
9
IC23C 74HC126E
74HC4049I
ST626X-EMU2 - ANNEX
29/38
33
34
File : PC07.SCH RP11 1 1 VCE RP14 VCE RP5 VCE 1 PC[0..7] PC[0..7] PC[0..7] PUPPC0 PUPPC7 PUPPC1 PUPPC2 PUPPC6 PUPPC5 PUPPC3 PUPPC4 10K-S10 10K-S10 10K-S10 2 3 4 5 6 7 8 9 10 OUTPC7 OUTPC6 OUTPC5 OUTPC4 OUTPC0 OUTPC3 OUTPC2 OUTPC1 TSPC7 TSPC6 TSPC5 TSPC4 TSPC0 TSPC2 TSPC1 TSPC3 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 11 1 IC27 CLK OC PPP P LLL L DDD D 111 1 AAA A 321 0 333366 12245668 IC9 11 1 IC19 CLK OC PUPCAD7 PUPCAD6 PUPCAD5 PUPCAD4 PUPCAD3 PUPCAD2 PUPCAD1 PUPCAD0 D7 D6 D5 D4 D3 D2 D1 D0 374E Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 PUPPC7 PUPPC6 PUPPC5 PUPPC4 PUPPC3 PUPPC2 PUPPC1 PUPPC0 GND18 17 14 13 8 7 4 3 19 16 15 12 9 6 5 2 IIIIIIII N NNN N NN N PPPPPPPP U UUU U UU U TTTTTTTT / C L K I/O I/O I/O I/O I/O 51 49 48 47 46 D5 INPC5 TSPC5 OUTPC5 PUPCAD5 EXT7 EXT8 1 2 EPM5128 57 56 55 53 52 D6 INPC6 TSPC6 OUTPC6 PUPCAD6 PUPCAD7 PUPCAD6 PUPCAD5 PUPCAD4 PUPCAD3 PUPCAD2 PUPCAD1 PUPCAD0 D7 D6 D5 D4 D3 D2 D1 D0 374E Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 19 16 15 12 9 6 5 2 GND18 17 14 13 8 7 4 3 I/O I/O I/O I/O I/O I/O I/O I/O 65 64 63 62 61 60 59 58 D7 RBB2 RBB1 RBB0 INPC7 TSPC7 OUTPC7 PUPCAD7 PCCAD7 PCCAD6 PCCAD5 PCCAD4 PCCAD3 PCCAD2 PCCAD1 PCCAD0 PCCAD[0..7] PCCAD[0..7] I/O I/O I/O I/O I I I I I I I I I I I I I I I I I/O //////// //////// O O O O O O O O O O OO O O OO 2 2222233 4 5678901 D 4 33444444 89012345 EXT[0..9] EXT[0..9] P OT I UUSN PT PP C P CC A C3 3 D3 3 R D P OT I B 3 UU S N B PT PP 3 CP CC AC4 4 D4 4 PLD1A4 W8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MW2X8C RP15 GND 10K-S10 1 VCC ITSI4 TIM1IN RBB[0..3] RBB[0..3] LVI RS9A 1K-4R8P 2 RS9B 3 4 5 RS10A 1 RS10B 4 3 6 1 234567890 RS9C 6 7 RS10C 5 8 RS9D 8 RS10D 7 1K-4R8P OUTPC0 OUTPC1 OUTPC2 OUTPC3 OUTPC4 OUTPC5 OUTPC6 OUTPC7 VR02091H 2
30/38
PORT C
PUPPC[0..7]
PUPPC[0..7]
OUTPC[0..7] TSPC[0..7]
OUTPC[0..7]
TSPC[0..7]
INPC[0..7]
INPC[0..7]
LATCH0 LATCH1 PLD1A[0..4]
PLD1A[0..4]
Figure 6. Port C and SIO
WRITE READ
NRESETI
ST626X-EMU2 - ANNEX
D[0..7]
D[0..7]
CLOCK
PUPCAD0 OUTPC0 TSPC0 INPC0
PRUN
ITSI4
D0
4 5 6 7 8 9 10 11
I/O I/O I/O I/O I/O I/O I/O I/O
PUPCAD1 OUTPC1 TSPC1 INPC1 D1
12 13 14 15 17
I/O I/O I/O I/O I/O
PUPCAD2 OUTPC2 TSPC2 INPC2 D2
18 19 21 22 23
I/O I/O I/O I/O I/O
TIMOUT
TOUT
LVI
VCE
VCC
R2 10K
R1 47K
IC12A
R3
1
GND
100K
74HC14
PUPPC[0..7] TSPC[0..7] PUPPC4 1 2 OUTPC4 2 74HC126E 74HC14E 2 IC21A 1 3 IC28A PC4 1 IC43A 74HC126E 1 RS1A 100K-4R8P 2 TSPC4 2 3 VCE 3 IC51A 74HC126E IC38A 1 74HC14E IC16A 2 3 INPC4 74HC4049I 3 RS1B 100K-4R8P 4 PC0 1 PC[0..7] PC[0..7]
PUPPC[0..7] TSPC[0..7] OUTPC[0..7]
OUTPC[0..7]
INPC[0..7] VCE
INPC[0..7]
PUPPC0
TSPC0
OUTPC0 3
1
2
INPC0
IC29A 2 3
IC20A 74HC126E 2
Figure 7. Port C and SIO buffers
74HC4049I
PUPPC1 VCE 12 11 IC51D 74HC126E OUTPC5 12 11 IC28D 74HC126E 12 1 3 IC38F 13 74HC14E VCE 5 TSPC6 OUTPC6 4 5 6 IC51B 74HC126E IC38B 3 74HC14E 7 RS1D 100K-4R8P 8 PC2 4 PUPPC6 VCE 5 IC16F 15 14 INPC5 74HC4049I 5 RS1C 100K-4R8P 6 PC1 TSPC5 12 VCE 1 3 1 3 11 IC43D 74HC126E IC21F 13 74HC14E 4
PUPPC5
TSPC1
OUTPC1 11
1 3
12
IC29F 15 14 INPC1 74HC4049I PUPPC2
IC20D 74HC126E 12
3 RS2B 100K-4R8P 4 PC5
TSPC2
OUTPC2 6
4
5
6 IC43B 74HC126E
INPC2
IC29B 4 5
IC20B 74HC126E 4
5 RS2C 100K-4R8P 6 PC6 6 IC21B IC28B 4 3 74HC126E 74HC14E
74HC4049I
IC16B 4 5 INPC6 74HC4049I PUPPC7
PUPPC3 VCE 9 1 0 8 IC38E 11 74HC14E 8 IC51C 74HC126E 1 0 VCE TSPC7 9 1 0 8 1 0 9 7 RS2D 8 IC28C 10 74HC126E 74HC4049I IC21E 11 74HC14E 100K-4R8P PC7 VR02091I OUTPC7 IC16E INPC7 12 11 8 IC43C 74HC126E
TSPC3
OUTPC3
9
1 RS2A 100K-4R8P 2 PC3
INPC3
12
IC29E 11
IC20C 74HC126E 10
74HC4049I
ST626X-EMU2 - ANNEX
31/38
35
36
IC1 PRUN 2 4 6 8 11 13 15 17 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 74HC244 2 OSCOUT IC52A 74HC126E IC35A 14 GND VCC R11 IC7 100K E N D B U I L D U P RR D AD0 MR DB 0B 0 WR RE IA TD E 11 10987654 88 2143 IIIIII ////// OO O O OO IIIIIIII //////// O OO O OO O O DR R E R 7 DA X E R MT S B D9 B B7 U I 7 L D U P 877777 098765 CEXT C8 10NF 15 REXT/CEXT 1 A Q 13 2 B 3 CLR Q4 74HC123 R12 1K 3 1 VCE 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 18 16 14 12 9 7 5 3 PRUN ROMADR TY2B TY9B CLKSYST INTRES CLOCK 1 19 GND W7 1 EXT 2 INT 3 MW1X3C CLOCK IIII N N NN P PPP U U UU TTTT / C L K D1 RDRBB1 RAMD1 NCERAM A4 RAMADD4 I/O I/O I/O I/O I/O I/O D6 RDRBB6 RAMD6 CLKSYSTNB A7 RAMADD7 RAMADD3 VCE R19 1K R21 1K 11 10 4 5 IIIIIIII //////// O OOO O O OO EPM5192 44445555 67890123 B B B E RRD NNN X A D4 K K K T MR 0 1 2 1 DB 04B 4 6 IC52B 74HC126E EXT[0..10] RDRBB[0..7] RDRBB[0..7] A6 RAMADD6 I/O I/O I/O I/O I/O I/O I/O I/O 12 13 14 15 16 17 74 73 72 71 70 69 68 67 W2 1 3 5 7 2 4 6 8 MW2X4C RAMADD0 OPTSER A5 RAMADD5 I/O I/O I/O I/O I/O I/O I/O I/O 65 64 63 62 20 21 22 23 IC18 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 RST Q3 Q2 CLK Q1 HC4040 VCKOUT CKNMI EXT[0..10] RAMPB[0..7] DRBB[0..7] 1 15 14 12 13 4 2 3 5 6 7 9 RAMADD1 PRUN D2 RDRBB2 RAMD2 TY2B D3 RDRBB3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IIIIII ////// O OO O OO 333333 345678 4444 1234 AA A A 0123 R ST BW A T Y NA M O9 K I D PB3 T 3 IIII NNNN PPPP UUUU TTTT 59 58 57 56 55 54 RAMADD2 CKBUILDUP D5 RDRBB5 RAMD5 25 26 27 28 29 30 31 32 D0 D1 D2 D3 D4 D5 D6 D7 1 GND RP25 VCC 1 RP26 11 12 13 15 16 17 18 19 RAMADD0 RAMADD1 RAMADD2 RAMADD3 RAMADD4 RAMADD5 RAMADD6 RAMADD7 BNK0 BNK1 BNK2 BNK3 RAMD0 RAMD1 RAMD2 RAMD3 RAMD4 RAMD5 RAMD6 RAMD7 10 9 8 7 6 5 4 3 25 24 21 23 2 NCERAM 20 26 RWRAM 27 22 10K-S10 10K-S10 IC14 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 CS1 CS2 WE OE CY7C185 VR02091L HARD SOFT W3 11 22 33 MW1X3C WATCHDOG
32/38
PRUN0
TY2 TY9
IC15A
OSCIN
3
2
4049I
ST626X-EMU2 - ANNEX
NRESETI EXTINT PULS
D[0..7]
D[0..7]
A[0..7]
A[0..7]
READ
READ
WRITE
WRITE
OPTSER
R8
1M XT2
8MHZ IC11A
IC11D
1
2
9
8
74HC04
74HC04
C5 22PF
C6 22PF
GND
GND
6
IC35B CEXT
7
REXT/CEXT
Figure 8. RAM, EEPROM, Bank reg., Data ROM windowing, watchdog, Reset
9 10 11
Q
5
GND
A B CLR 74HC123
Q 12
RSTINT STOP WAIT
CLOCK PLD1A[0..4] PLD1A[0..4] PLD1A0 PLD1A1 PLD1A2 PLD1A3 PLD1A4 VCC 1 RP9 10K-S10 F0 F1 F2 F3 F4 F5 F6 F7 198765432 0 INT[0..4] INT[0..4] 9 7 INT0 INT1 INT2 INT3 INT4 NRESETI GND 2 15 1 CLK QH INH SH/LD 74HC165 F0 F1 F2 F3 F4 F5 F6 F7 15 16 17 18 19 20 21 22 W6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MW2X8C 10 11 12 13 14 3 4 5 6 IC17 SER A B C D E F G H QH 15 16 17 18 19 20 21 22
CLOCK
A[0..7]
A[0..7]
A0 A1 A2 A3 A4 A5 A6 A7
TY9B
1 2 3 4 5 6 7 8 9 10 11 13 14 23
IC5 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 20V8
RESTO RESSO NITPB NITTIM1 ITSI4 NITTIM1 NITADC NITTIM2 VCE ITRTC PRUN VCKOUT R15 100K IC26B 10 11 12 13 14 3 4 5 6 2 15 1 1 098765432 GND 1 VCC 10uH L2 VCC 15 10 1 C15 10uF 2 C14 100NF 2 D1 1N4004 1 1 VCC C16 2 10uF C21 100NF R25 100K 4 R20 10K GND C17 1uF 3 2 1 1 IC57A 1 LM324
ITSI4 NITTIM1 NITADC NITTIM2 ITRTC
1 2 3 4 5 6 7 8 9 10 11 13 14 23
IC15C
IC2 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 20V8
Figure 9. Control and interface power
CKNMI
3
4
7
6
VCE GND RP27 10K-S10
74HC14E READ WRITE RSTINT
4049I
IC34 SER A B C D E F G H QH CLK QH INH SH/LD 74HC165
9 7 VCC
W5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MW2X8C
OPTSER
R18 100K
IC26A
IC15B
F0 F1 F2 F3 F4 F5 F6 F7
15 16 17 18 19 20 21 22
NRESETAP
1
2
5
4
D2 1N4148
4049I
1 2 3 4 5 6 7 8 9 10 11 13 14 23
74HC14E LVI EXTRES BDIO EXWR VCC 14 11
IC3 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 20V8
D3 1N4148
VDDI
1 24
V1 +VIN +VIN
+VOUT +VOUT
R26 1K
12 13
GND C12 100nF 100nF C18 C13 470uF-EA
-VIN -VIN VSRC
-VOUT -VOUT
GND Q1 BD233
VCE
VCE L1 56uH 8 SW IN SW OUT CT C19 470pF 3 2 R24 680 VR02091E 7 IPK COMP MC34063 5 IC56 DR IN 1 BYV10-20 D4 15K R22 R23 1,5K R14 10K
0,330 R17
330 R16
GND
VCC
DC/DC CONVERTER
VCCAPP
ST626X-EMU2 - ANNEX
33/38
37
38
2 4 6 8 11 13 15 17 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 -12V -12V AINB C11 10uF 4 IC50A 2 3 TL072A 8 +12V R13 470 1 PA4 PA5 PA6 PA7 2 4 8 10 18 16 14 12 9 7 5 3 1 19 1G 2G 74HC244 IC55 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 PA0 PA1 PA2 PA3 O1 O2 O3 O4 1 3 9 11 13 5 6 12 IC59 I1 I2 I3 I4 C1 C2 C3 C4 2 4 8 10 1 3 9 11 13 5 6 12 4066EC GND C9 10uF +12V 4066EC IC58 I1 O1 I2 O2 I3 O3 I4 O4 C1 C2 C3 C4 PB0 PB1 PB2 PB3 O1 O2 O3 O4 C10 2.2nF 2 4 6 8 11 13 15 17 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 GND PB4 PB5 PB6 PB7 2 4 8 10 18 16 14 12 9 7 5 3 1 19 GND 1G 2G 74HC244 IC30 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1 3 9 11 13 5 6 12 2 4 8 10 IC31 I1 I2 I3 I4 C1 C2 C3 C4 1 3 9 11 13 5 6 12 4066EC D0 D1 D2 D3 D4 D5 D6 D7 VI+ VICLKR CLK EOCN GND 2 4 8 10 1 2 3 5 6 7 19 4 9 8 CS RD VREF WR INTR AGND ADC0802C AIND VSREF VCE 4066EC IC47 I1 O1 I2 O2 I3 O3 I4 O4 C1 C2 C3 C4 18 17 16 15 14 13 12 11 IC6 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 R4 1K R5 1K PC0 PC1 PC2 PC3 O1 O2 O3 O4 1 3 9 11 13 5 6 12 2 4 6 8 11 13 15 17 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 PC4 PC5 PC6 PC7 2 4 8 10 18 16 14 12 9 7 5 3 1 19 1G 2G 74HC244 IC36 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 IC37 I1 I2 I3 I4 C1 C2 C3 C4 GND EOCADC 1 3 9 11 13 5 6 12 4066EC 4066EC IC44 I1 O1 I2 O2 I3 O3 I4 O4 C1 C2 C3 C4 VR02091C
34/38
PA[0..7]
PA[0..7]
PACAD0 PACAD1 PACAD2 PACAD3 PACAD4 PACAD5 PACAD6 PACAD7
PACAD[0..7]
PACAD[0..7]
ST626X-EMU2 - ANNEX
GND
Figure 10. Analog To Digital Converter
PB[0..7]
PB[0..7]
PBCAD0 PBCAD1 PBCAD2 PBCAD3 PBCAD4 PBCAD5 PBCAD6 PBCAD7
PBCAD[0..7]
PBCAD[0..7]
PC[0..7]
PC[0..7]
PCCAD0 PCCAD1 PCCAD2 PCCAD3 PCCAD4 PCCAD5 PCCAD6 PCCAD7
PCCAD[0..7]
PCCAD[0..7]
R10
GND
GND
1K
D[0..7]
D[0..7]
NADCRRR NSTARTADC ADCCLOCK ADCCLOCK VSREF VSREF
PA[0..7]
PA[0..7]
ST2626X and ST629X PROBE CONNECTORS
PB[0..7] Number of component's pin
PB[0..7]
PC[0..7]
PC[0..7]
PB6 PB7
VCCAPP
GND
Figure 11. Application connectors
XTAL EXTAL
PA0 VCCAPP GND PA1 PA2 PA3 PA4 PA5 PA6 PA7 XTAL EXTAL CKNMI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB5 PB4 PB3 PB2 TST PB1 PB0 PC0 PC1 PC2 PC3 PC4 CKNMI NRES
NRES
NRES GND
J1 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 HE1034DM
J2 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 34 33 HE1034DM
VSREF
VSREF VSREF PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 GND
VCCAPP PC1 XTAL EXTAL CKNMI PC7 PC6 PC5 PC4
NRES PB7 PB6 PB5 GND
J3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 HE1034DM ST2621X PROBE CONNECTORS
J4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 HE1034DM
GND
VSS
VR02091D
ST626X-EMU2 - ANNEX
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r esonnat eur GD N G ND
2
C3 470PF
TP3 TP4 TP5 C4 1NF C D1 100NF
1
40
VSREF G ND VCCAPP PC 1 XTAL EXTAL CKNM I PC7 PC6 PC5 PC4 NR ES PB7 PB6 PB5 G ND J3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 HE10-34DM PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 ST2 6 2 0 X/ 1 X/ 2 X P R OB E J4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 HE10-34DM G ND PA1 PA2 PA3 VCCAPP PC1 OSCIN OSCOUT CKNMI VSS PA0 PA1 PA2 PA3 PA0 PA1 PA2 PA3 1 2 3 4 5 VCCAPP PC1 OSCIN OSCOUT CKNMI PC7 PC6 PC5 PC4 NRES PB7 PB6 PB5 20 19 18 17 16 U2 VDD TIM OSCIN OSCOUT NM I G ND GD N PB0 PB1 PB3 PB5 NRES PB7 PB6 PB5 6 7 8 9 10 VPP/TEST RESET PB7 PB6 PB5 DIL20 PB0 PB1 PB2 PB3 PB4 PB0 PB1 PB2 PB3 PB4 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 U 3 VDD T IM OSCIN OSCOUT NI M PC 7 PC 6 PC 5 PC 4 VPP/TEST R ESET PB7 PB6 PB5 DIL28 VSS PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 1 U4B 3 5 74HC04 6 1K C2 100PF VCC GND VCC G ND R4 100K C1 EXTAL 100NF C 100PF GND 9 74HC04 U4D 8 OSCOUT TP1 MW1X1C TP2 MW1X1C 74HC04 OSCIN R5 3.3 VCC 4 U4C MW 2X1C G ND W2 2 R1 XTAL W1 11 22 33 MW3X1C
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6.3 PROBE
VCC
VDD
VCCAPP
ST626X-EMU2 - ANNEX
G ND
VSS
Figure 12. Probe for ST620x, ST621x, ST622x
VCCAPP OSCIN OSCOUT CKNMI
1 2 3 4
U 1 VDD OSCIN OSCOUT NI M
VSS PA1 PA2 PA3
16 15 14 13
N RES PB7 PB6
5 6 7 8
VPP/TEST R ESET PB7/AIN3 PB6/AIN2
PB0 PB1 PB3 PB5/AIN1
12 11 10 9
DIL16
U4A
1
2
74HC04 R4
10M
XT1
8MHZ-XT-P
G ND
GN D
28 P0 C P1 C P2 C P3 C P4 C
VC C PA7 PA6 PA5 PA4 PA3
P B6 P B7 PA0 VCC APP VSR EF PA1 PA2 PA3 PA4 PA5 PA6 PA7 XTAL EXTAL PB6 PB7 PA0 W 1 2 M 2X1C W G1 G UTTECO O NTACT W 2 1 2 M 2X1C W G 2 G UTTEO O UVER TE
PB0 PB1 PB2 PB3 PB4 PB5 PB6/TIM 2I PB7/TIM 2O PA0/ADC VCCAPP VSREF PA1/ADC PA2/ADC
P I N P ROB E U 1 1 1 28 2 2 27 3 3 26 4 4 25 5 5 24 6 6 23 7 7 22 8 8 21 9 10 9 20 11 10 19 12 11 18 13 12 17 14 13 16 14 15 DIL28 PB 5 PB 4 PB 3 PB 2 PB 1 PB 0 P0 C P1 C P2 C P3 C P4 C N I/C U M KO T NE RS 1 PC 2 PC 3 PC 4 J2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 HE10-34DM GD N
CONN E C T ORS 28 PC0/ADC 27 PC1/TIM 1/ADC 26 PC2/SI/ADC 25 PC3/SO/ADC 24 PC4/SK/ADC 23 22 NR S E 21 O UT SCO 20 O SCIN 19 PA7/ADC 18 PA6/ADC 17 PA5/ADC 16 PA4/ADC 15 PA3/ADC
GD N
J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 H E10-34D M 20
VSR EF PB 6 PB 7 PA0 PA3 PA2 PA1
Figure 13. Probe for ST625x, ST626x, ST629x
GD N
PB0 PB1 PB2 PB3 PB6/TIM 2I PB7/TIM 2O PA0/ADC VCCAPP VSREF
P I N P ROB E U2 1 1 20 2 2 19 3 3 18 4 4 17 5 5 16 6 7 6 15 8 7 14 9 8 13 10 9 12 10 11 DIL20
CONN E C T ORS 20 PC2/SI/ADC 19 PC3/SO/ADC 18 PC4/SK/ADC 17 16 NR S E 15 O UT SCO 14 O IN SC 13 PA3/ADC 12 PA2/ADC 11 PA1/ADC
16
P I N P ROB E C ONN E C T ORS
VCC VCC
TP 5
TP 4
PB0 PB2 PB3 PB6/TIM 2I PB7/TIM 2O VCCAPP VSREF PC 2 PC 3 NR S E O UT SCO O IN SC PA5 PA4
1 2 3 4 5 6 7 8
GD N
U3 1 16 2 15 3 14 4 13 5 12 6 11 7 10 89 DIL16 16 15 14 13 12 11 10 9
1 M 2X1C W GD N U 4C R5 6 74HC04 GD N 1K XTAL C2 100PF 5 4
W 4 2
U4A
U4B
1
2
3
C 1 EXTAL 100N F C 100PF GD N 9
U 4D 8 74HC 04 O OT SC U
74H C04 R 3 OC S IN W 3 11 22 33 M 3X1C W
74HC 04
10M
R 4 3.3
XT1
8MH Z-XT-P
C 3 470PF
P2 T P1 T TP 3
reso ate nn ur
C 4 1N F
GD N
GD N
GD N
ST626X-EMU2 - ANNEX
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ST626X-EMU2 - ANNEX
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)1998 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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